发明名称 |
METHOD OF FACILITATING THREE-DIMENSIONAL DEVICE LAYOUT |
摘要 |
PROBLEM TO BE SOLVED: A device layout has a device structure including a first device and a second device formed thereon, and an active region of the second region is located inside the upper surface so as to facilitate a three-dimensional device layout. SOLUTION: For example, a highly doped N<+> polylayer is next formed on the surface. This polylayer is planarized up to an upper surface of a gate 895 to form a bit-line contact area 110. An MO dielectric layer is layed to expose the contact area 110. A metal layer 150 is next deposited so as to fill an contact opening 120. This metal layer 150 is etched for forming a bit-line conductor. The capacity of spatially positioning a device on a trench allows a more effective three-dimensional layout. As a result, the density of a device for a prescribed area can be increased. |
申请公布号 |
JPH1074907(A) |
申请公布日期 |
1998.03.17 |
申请号 |
JP19970165764 |
申请日期 |
1997.06.23 |
申请人 |
SIEMENS AG;INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
HAMMERL ERWIN;MANDELMAN JACK A;POSCHENRIEDER BERNHARD;SHORT ALVIN P;SRINIVASAN RADHIKA;STENGL REINHARD J;HO HERBERT L |
分类号 |
H01L27/00;H01L21/822;H01L21/8242;H01L27/04;H01L27/108 |
主分类号 |
H01L27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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