发明名称 |
METHOD FOR FORMING CONNECTION PART AND SEMICONDUCTOR CHIP |
摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM cell laminated capacitor in self-alignment with the bit line. SOLUTION: A bit line on a support circuit 52 of a chip and a thick insulating body 58 on a mutual connection wiring 50S are provided with uniform topology, acting to give a self-alignment between a capacitor 108a and a bit line 50a. The bit line 50a and a support circuit mutual connection wiring 50S and formed of metal of the same level, however, patterned in separate masking processes. The laminated capacitors 108a are mutually separated by a distance shorter than the minimum dimension of a photolithographic system used for production. |
申请公布号 |
JPH1074909(A) |
申请公布日期 |
1998.03.17 |
申请号 |
JP19970187927 |
申请日期 |
1997.07.14 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
JOHN EDWARD KURONIN;CARTER UERINGU KAANTA;BRIAN JOHN MACHIESUNII |
分类号 |
H01L27/04;H01L21/02;H01L21/822;H01L21/8242;H01L27/108 |
主分类号 |
H01L27/04 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|