发明名称 |
Semiconductor memory device that can read out data at high speed |
摘要 |
A phi C generation circuit provides a column address buffer control signal to a column address buffer so that the column address buffer maintains a latch operation during the operation period of a differential amplifier. The column address buffer responds to a column address buffer control signal to latch an input address signal for providing a column address signal to a phi D and PAE generation circuit. The phi D and PAE generation circuit provides a differential amplifier activation signal to the differential amplifier according to a column address signal and a column access activation signal. The differential amplifier responds to a differential amplifier activation signal for amplifying data applied from a data input and output line to provide the same to a selector via a readout data line.
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申请公布号 |
US5729502(A) |
申请公布日期 |
1998.03.17 |
申请号 |
US19960775762 |
申请日期 |
1996.12.31 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
FURUTANI, KIYOHIRO;MIYAMOTO, HIROSHI |
分类号 |
G11C11/401;G11C7/22;G11C11/4076;G11C11/409;G11C11/4093;G11C11/4096;(IPC1-7):G11C8/00 |
主分类号 |
G11C11/401 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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