| 摘要 |
A frequency multiplication circuit (10) includes a periodic interval selector (12) and a delay element (28) to produce an output signal (26) in phase with, and at a frequency multiple of a reference signal (18). During a first time interval, the periodic interval selector (12) bases the output signal (26) on the reference signal (18). During a second time interval, the periodic interval selector (12) bases the output signal (26) on a delayed signal (22) produced by the delay element (14) based upon the output signal (26). Feedback from the output of the periodic interval selector (12) through the delay element (14) and the operation of the periodic interval selector (12) causes the output signal (26) to be in phase with, and at a frequency multiple of the reference signal (18). Delay adjuster (52) adjusts delay produced by the delay element (14) to adjust the output signal (26) to cause the output signal (26) to have a desired duty cycle consistency. Periodic interval selector (12) and delay adjuster (52) may be adjusted as well as to adjust a frequency multiplication ratio of the frequency multiplication circuit (10). Delay element (14) may be implemented with digital circuit elements such as inverters, other logic gates, or individual circuit elements operably coupled to produce a controllable variable delay.
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