Verfahren und Vorrichtung zur Optimierung des Abschaltvorgangs eines nichteinrastenden, abschaltbaren Leistungs-Halbleiterschalters

摘要

This invention concerns a process for optimizing the power-down cycle of a non-engaging, interruptable power semiconductor switch (2) in a saturating power converter and a device for carrying out the process. According to the invention, when the interrupt signal (Saus) arrives, the gate emitter voltage (UGE) of this power-semiconductor switch (2) lowered with the help of a maximally permissible discharge current and its collector-emitter voltage (UCE) are monitored against exceeding a reference voltage (UCEref), the value of which is set so that the collector current (IC) begins to commutate, and upon reaching the reference value (UCEref), the discharge current is reduced to a value which is below the value of the maximum permissible discharge current. Thus, the power-down cycle of a non-engaging, interruptable power semiconductor switch (2) is largely optimized, so that the voltage rise and current drop times can be separately controlled.