发明名称 Phase locked loop with a charge pump current limiting arrangement
摘要 The PLL has charge pump which charges and discharges a capacitive filter as a function of charge and discharge control signals (HIGH,LOW). The control signals are modified at the output (HIGH3,LOW3) by a limiter unit. The limiter unit has two window circuits (840,860), one each for the high and low states. The window circuits limit the duration of the control signals when the PLL is in a locked state. The value of the charge and discharge current is limited when the PLL is not in a locked state.
申请公布号 EP0828350(A1) 申请公布日期 1998.03.11
申请号 EP19970410100 申请日期 1997.09.09
申请人 STMICROELECTRONICS S.A. 发明人 LEBOULEUX, NICOLAS;BERGER, PHILIPPE;CIROT, ERIC
分类号 H03L7/089;H03L7/095;H03L7/107;H04N5/12;(IPC1-7):H03L7/089 主分类号 H03L7/089
代理机构 代理人
主权项
地址