| 摘要 |
PCT No. PCT/JP94/01478 Sec. 371 Date Oct. 25, 1995 Sec. 102(e) Date Oct. 25, 1995 PCT Filed Sep. 7, 1994 PCT Pub. No. WO95/09391 PCT Pub. Date Apr. 6, 1995A minimum/maximum data detector for rapidly detecting the minimum or the maximum data from a plurality of numeric data. In FIG. 1 , one of consecutive numeric data stored in memory 1 is read out by an address designated by a register 2, and is transferred to registers 5 and 6. A counter 9 counts up the number of numeric data which have been stored in register 6. The contents of the registers 5 and 11 are compared by a circuit 4. When detecting minimum data, if the contents of the register 5 are judged to be smaller, the contents of the register 6 and the counted results of the counter 9 are linked in an index linking circuit 10. The linked result is then stored in the specific register 11. The content of the register 2 is incremented by "1" whenever the comparison is executed. Once the read out of one series of consecutive numeric data have been completed, then the numeric data remaining in the specific register 11 is the minimum data. The address of the minimum data in the memory 1 can be obtained by adding the index (counted results) and the top address utilized at the beginning of the detection.
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