| 摘要 |
PROBLEM TO BE SOLVED: To decrease density of interconnection by bringing a first interconnection layer into electrical contact with a first impurity diffused region through a first contact hole and bringing a second interconnection layer simultaneously into electrical contact with a second impurity diffused region and a predetermined part of a wafer through a second contact hole. SOLUTION: A gate insulation layer 25 and a gate 26 are formed on a semiconductor layer between field oxides 24 and impurity diffused regions 27a, 27b are formed in the semiconductor layer on the opposite sides of the gate 26. An interlayer insulator 28 is then deposited thereon and contact holes 29a, 29b are made therein by etching. After removing a mask pattern, a metal layer is deposited on the interlayer insulator 28 while filling the contact holes 29a, 29b. Finally, a first metallization layer 30a coming into contact with an exposed impurity diffused region 27a and a second metallization layer 30b coming into contact with an exposed impurity diffused region 27b and a wafer 21 are formed by patterning the metal layer 28.
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