| 摘要 |
PROBLEM TO BE SOLVED: To provide an automatic lock circuit low in jitter independently of process fluctuation, capable of warranting automatically locking of a PLL to an object frequency and maintaining the locking over a wide operation temperature range. SOLUTION: A lock detector 160 detects a lock state based on a phase difference of a reference frequency and a division frequency of a VCO 140. A strobe circuit 180 strobes a signal FLS to generate a coarse lock signal CLS. The signal CLS denoting a level '1' indicates a lock state and whether or not the PLL is actually locked depends on an output voltage of a voltage comparator 24 and a signal OLS is outputted from an AND gate 190. The operation of an n-bit counter 250 is specified by the signal OLS and each count specifies a sole frequency range of the VCO. The 1st count state is set and the 'usual PLL operation' is started. When the PLL is not locked at a fixed time td, the count output is changed. This processing is repeated till locking is attained. |
