| 摘要 |
PROBLEM TO BE SOLVED: To enhance a data output speed by making the cell array of 2B bits to be cell units of 2X<+> Y pieces while dividing them into 2X and 2Y in horizontal and vertical directions and by dispersedly arranging banks of 2B<-> X<-> Y bits in respective cell units to provide many banks while reducing the increasing of the area of chips. SOLUTION: For example, in the case of constituting memory elements of 2<24> bits by four blocks provided with cell arrays of 2<21> bits at both sides around row decoders, each array is bisected in the horizontal and vertical directions to produce four cell units of 2<19> bits and the cell array divided into cell units is divided into cell bundles of 2<19> bits to produce banks respectively operate mutually and independently. That is, the whole of the memory cells has four banks 0-3 comprising cells 2<22> bits and the banks 0-3 are evenly dispersed in respective cell arraies as cell bundles of 2<19> bits. Thus, the entire area of data busses is made small and the data output speed is enhanced. |
