发明名称 IMPRINT COMPENSATING METHOD AND CIRCUIT FOR FERROELECTRIC SEMICONDUCTOR MEMORY DEVICE
摘要 <p>PROBLEM TO BE SOLVED: To provide a circuit for compensating in-print of a ferroelectric capacitor in a ferroelectric memory. SOLUTION: This imprint compensating circuit has a first compensation control section 24 which transmits column lines 62, 64 to storage electrodes 38a, 42a as a fixed potential by sensing voltage of a pad 6 and controlling a column decoder 16 and sense amplifiers 48, 50, generates in-print compensation voltage by a pulse generation section 20 and transmits it to plate electrodes 38b, 42b, and a second compensation control circuit 28 which transmits a fixed potential to a plate electrode by sensing voltage of a pad 8 and controlling a pulse generating section 20, transmits voltage provided to a data pad 10 to a column line by writing operation, amplifies it by a sense amplifier, and transmits it to a storage electrode as imprint compensation voltage.</p>
申请公布号 JPH1069789(A) 申请公布日期 1998.03.10
申请号 JP19970126937 申请日期 1997.05.16
申请人 SAMSUNG ELECTRON CO LTD 发明人 DEN HEIKICHI
分类号 G11C14/00;G11C11/22;(IPC1-7):G11C14/00 主分类号 G11C14/00
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