发明名称 BUFFER ARRANGING DEVICE IN ATM SYSTEM
摘要 PROBLEM TO BE SOLVED: To reduce the signal processing scale and the device scale of a peripheral circuit by reducing the capacity of a format conversion buffer making transmission ATM cell order strings at an active system and a reserved system coincident with each other to the degree of several cells and simplifying the peripheral circuit. SOLUTION: The reading side of a format conversion buffer 14 in an active system format conversion part A2 does not read ATM cell data by means of the over head part of an SDH frame but buffers ATM cell data at a fixed speed. In addition, the reading side of an SW buffer 4 in an active system SW part A1 generates a dummy cell equivalent to the fixed speed. The buffer 14 abolishes a dummy cell by a writing side to continuously read and read out all the cells except for the dummy cell.
申请公布号 JPH1070550(A) 申请公布日期 1998.03.10
申请号 JP19960227132 申请日期 1996.08.28
申请人 NEC CORP 发明人 MIYAMOTO AKIHIRO
分类号 H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 主分类号 H04Q3/00
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