发明名称 Memory module assembly using partially defective chips
摘要 Methods and devices for using less-than-perfect memory chips and packages in the manufacture of memory modules. In the preferred method the failed I/O lines in primary memory packages are disconnected and replaced by selected I/O lines from flawless or partially defective backup parts (28) all mounted on the same module. The various processes comprise sorting of partially defective parts according to the results of wafer or packages test (18), judicious distribution of backup parts on a PC board module and routing of their I/O lines (21), optimized patching techniques (25) and multi-level tests and repatching routines. The methods and processes are equally applicable to Chip On Board assemblies as well as package assemblies.
申请公布号 AU4149897(A) 申请公布日期 1998.03.06
申请号 AU19970041498 申请日期 1997.08.12
申请人 CHARLES I. PEDDLE;INTERCELL CORPORATION 发明人 CHARLES I. PEDDLE
分类号 G11C29/00;G11C29/44 主分类号 G11C29/00
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