发明名称 SYNCHRONOUS GRAPHIC RAM HAVING BLOCK WRITE CONTROL FUNCTION
摘要 PROBLEM TO BE SOLVED: To control an enable interval of column decoder to realize stable block write by switching over the first and second delay means formed of a plurality of adjustable inverters with a block write signal. SOLUTION: A switching means 50 transmits, depending on a block write/BW signal, an output of an inverter INT51 to a first transmission gate MN1, MP1. Moreover, it is then transmitted to a second delay means 52 via a second transmission gate NM2, MP2. In addition, the final output of the second delay means 52 is fed back and then re-input to an input end node 3 of the first delay means 51. Moreover, each delay means 51, 52 is respectively formed of an inverter INT51-1, 51-2 and INT52-1 to 52-4 and the number of inverters can be adjusted depending on necessity. Thereby, during the block write operation mode, enable interval of the column decoder can be gently controlled to make possible the stable block write operation.
申请公布号 JPH1064258(A) 申请公布日期 1998.03.06
申请号 JP19970164705 申请日期 1997.06.20
申请人 HYUNDAI ELECTRON IND CO LTD 发明人 RYU SHOKAKU
分类号 G11C11/407;G11C7/10;G11C8/10;G11C11/401;G11C11/409;G11C11/4091;G11C11/41;G11C11/413;H01L21/8242;H01L27/108 主分类号 G11C11/407
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