| 摘要 |
PROBLEM TO BE SOLVED: To provide a PLL circuit in which a lock up speed is improved while preventing a deteriorated C/N characteristic. SOLUTION: A reference frequency divider 22 generates a reference signal fr. A phase comparator 24 compares the phase of the reference signal fr with the phase of a comparison signal fp, and a charge pump 33 converts the output signal of the phase comparator 24 into a voltage signal. A low-pass filter 34 filters the output signal of the charge pump 33. A voltage controlled oscillator 37 provides the output signal fvco based on an output voltage of the filter 34. A comparison frequency divider 28 frequency-divides the output signal fvco to provide the output of the comparison signal fp. Storage devices 25, 26 store data of frequency division ratios DA. A frequency-division ratio changeover device 23 provides the output of the stored data in the storage devices 25, 26 to the reference frequency divider 22 and the comparison frequency divider 28 and also provides the output of the data with a decreased frequency division ratio DA in the case that the stored data are switched so that the frequencies of the reference signal fr and the comparison signal fp are increased by equal multiplication. |
