| 摘要 |
PROBLEM TO BE SOLVED: To provide a date generating circuit extremely limiting count delay by dividing a least significant counter and inserting an inverter circuit between them. SOLUTION: Corresponding to a reset pulse from a pulse circuit 9, counters 1a, 1b, 3 and 4 are cleared. Then, when respective counter outputs become 'L' and the output of the counter 1a becomes 'L', that output is turned to 'H' by the operation of an inverter 2 and the counter for one day is instantaneously changed from '0' to '1'. Afterwards, the circuit is functioned as a decimal counter to count up per day. When the count value becomes '366', the pulse is generated from the pulse circuit 9 and the similar operation is repeated. |
