| 摘要 |
PROBLEM TO BE SOLVED: To provide a high throughput and reduce the chip area by forming high withstand voltage elements and control elements on the same impurity region wherein only one conductivity type region exists between the high withstand voltage element and control element. SOLUTION: Only an n-type region of an n<-> epitaxial layer 3 exists between a high withstand voltage p-channel MOSFET element 10A and control element 30. An insulation layer 23 is formed to cover these elements 10A, 30 to result in that no p-type isolated diffusion region 5 to be a substrate potential region exists and hence wiring layers (gate electrode layer 17, source electrode layer 25a) for connecting the high voltage elements 10A and control element 30 never pass over the diffusion region 5. This greatly reduces the film forming time of the insulation layer 23 to obtain a high throughput. Because of no need for providing the diffusion region, the occupied plane area can be reduced. |
