发明名称 Multiple phase clock generator
摘要 The clock generator receives an external clock signal and generates several internal clock signals of mutually different phases. The clock generator has a control unit for controlling the duty cycle of the internal clock signals in synchronism with an oscillator output signal. The circuit arrangement includes a fixed phase feedback circuit, or a phase locked loop for generating the clock signals. The control unit can set fixed duty cycles for the internal clock signals. It can allow the internal clock signal duty cycles to differ from each other.
申请公布号 DE19736898(A1) 申请公布日期 1998.03.05
申请号 DE19971036898 申请日期 1997.08.25
申请人 NEC CORP., TOKIO/TOKYO, JP 发明人 SUGASAWA, YASUO, KUMAMOTO, JP
分类号 H03K21/10;G06F1/06;H03K5/15;H03L7/08;H04L7/033;(IPC1-7):H03K5/15 主分类号 H03K21/10
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