发明名称 Dreidimensionale gestapelte LSI.
摘要 Disclosed is a three-dimensionally stacked LSI having a plurality of integrated-circuit layers stacked together, each of which is equipped with a plurality of circuit elements (2, 10, 16). Each of the circuit elements are equipped with a power terminal (4) of its own, which is connected through interlayer via-hole wiring (22) to the power wiring of the uppermost integrated-circuit layer. The power wiring of the uppermost integrated-circuit layer is formed of a metal exhibiting a low electrical resistance, for example, Al, whereas the metal wirings of the other layers, which are exposed to high temperatures when forming the upper layers, are formed of W.
申请公布号 DE68918066(T3) 申请公布日期 1998.03.05
申请号 DE1989618066T 申请日期 1989.12.23
申请人 MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA, OSAKA, JP 发明人 TOMITA, YASUHIRO, NEYAGAWA-SHI, JP;TAKAGI, YOSHIYUKI, ASAHI-KU OSAKA-SHI, JP;AKIYAMA, SHIGENOBU, HIRATAKA-SHI, JP;YAMAZAKI, KENICHI, NISHIYODOGAWA-KU OSAKA-SHI, JP
分类号 H01L23/48;H01L23/528;H01L27/06;(IPC1-7):H01L25/065 主分类号 H01L23/48
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