| 摘要 |
<p>PURPOSE:To synchronize plural data processing parts with each other by including a clock generating means for generating at least one clock signal synchronized in phase with an original clock signal in each data processing part constituting this data processor. CONSTITUTION:At the time of receiving an original clock signal (K) 1011, a clock generator 101 can generate non-overlapped two-phase clock signals (K1, K2) with fixed duty which are in phase-synchronism with the same frequency as the signal K. Namely clocked inverter 1334 controlled by an external signal 1337 and a signal 1338 obtained by inverting the signal 1337 by an inverter circuit 1335 selects a signal 1309 when the signal 1337 is 'High' or selects the signal 1011 when the signal 1337 is 'Low' as an input of a two-phase clock generator 1305. Phases of signals K1, K2 are shifted from that of the signal 1011 by 90 deg. because the inverter 1334 is used.</p> |
