发明名称 |
Semiconductor device with circuit for preventing latch-up |
摘要 |
<p>Semiconductor device has a substrate bias generating circuit for generating a substrate bias to be applied to a p-type semiconductor substrate, a CMOS circuit formed on the semiconductor substrate and a latch-up protection circuit. The latch-up protection circuit has an n-type first region, a highly doped n-type second region, a p-type third region apart from the second region in the first region and a n-type fourth region surrounding said first region formed apart from the first region on the surface of the substrate. The second region is coupled with a power supply Vcc, the third region is coupled with an input line, the fourth region is coupled with a ground Vss, and the substrate is coupled with the substrate bias generating circuit.</p> |
申请公布号 |
EP0827206(A2) |
申请公布日期 |
1998.03.04 |
申请号 |
EP19970114366 |
申请日期 |
1997.08.20 |
申请人 |
OKI ELECTRIC INDUSTRY CO., LTD. |
发明人 |
KATO, KATSUHIRO;KIKUCHI, HIDEKAZU |
分类号 |
G11C11/34;H01L21/822;H01L21/8238;H01L27/02;H01L27/04;H01L27/092;(IPC1-7):H01L27/092 |
主分类号 |
G11C11/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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