High-density wirebond chip interconnect for multi-chip modules

摘要

A multi-chip module including a multi-layer substrate and a patterned metallization layer formed on each layer of the substrate. A multi-tiered cavity is formed with an integrated circuit (IC) mounting surface at the bottom of the multi-tiered cavity. A plurality of ICs are mounted on the IC mounting surface of the cavity. A first set of wire bonds extends from at least one IC to the exposed portions of patterned metallization of at least two tiers of the multi-tiered cavity. A second set of wire bonds extends from the at least one IC to bond pads of an adjacent IC. A third set of wire bonds extends from the at least one IC to bond pads of the adjacent IC such that the third set of wire bonds has a higher loop height than the second set of wire bonds.