发明名称 |
ARRANGEMENT WITH MASTER AND SLAVE UNITS |
摘要 |
The arrangement has a master unit connected to slave units via a bus. Each slave unit has an associated memory to which the master unit has read and/or write access. Each slave unit has a protocol region (1,2) via which the master unit indicates to the slave unit a desired access. - The slave unit uses this protocol region to grant or refuse access. In the event of access being granted the master unit assigns a memory address region whose position (adr30) it reads from the protocol region. |
申请公布号 |
HUT77275(A) |
申请公布日期 |
1998.03.02 |
申请号 |
HU19970002013 |
申请日期 |
1995.06.06 |
申请人 |
SIEMENS AG. |
发明人 |
ABERT,MICHAEL;KUEHLERS,JUERGEN;RENSCHLER,ALBERT |
分类号 |
G06F1/00;G06F13/42 |
主分类号 |
G06F1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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