发明名称 Phase/Frequency Detector
摘要 PFD includes UP and DOWN signal modules, and RESET signal module. UP and DOWN signal modules transmit UP and DOWN signals according to reference and fed-back clock signals. RESET module includes UP-RESET and DOWN-RESET signal modules. UP-RESET signal module resets UP signal module according to pre-trigger fed-back signal, UP and DOWN signals. Pre-trigger fed-back signal is generated according to original fed-back clock signal and calculation of logic gates and inverting delay module. DOWN-RESET signal module resets DOWN signal module according to pre-trigger reference signal, UP and DOWN signals. Pre-trigger reference signal is generated according to original reference clock signal and calculation of logic gates and inverting delay module.
申请公布号 US2010019802(A1) 申请公布日期 2010.01.28
申请号 US20080252329 申请日期 2008.10.15
申请人 HUANG HSIEN-SHENG;CHANG FENG-CHIA 发明人 HUANG HSIEN-SHENG;CHANG FENG-CHIA
分类号 H03D13/00 主分类号 H03D13/00
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