ERASE METHOD FOR PAGE MODE MULTIPLE BITS-PER-CELL FLASH EEPROM

摘要

An improved erasing structure for performing a programming back operation and a concurrent verify operation subsequent to application of an erasing pulse in an array of multiple bits-per-cell flash EEPROM memory cells is provided. A memory core array (12) includes a plurality of memory cells and an erase verify reference cell array for generating an upper erased state threshold voltage level. A pre-charge circuit (36a) is used to pre-charge all the array bit lines to a predetermined potential prior to a programming back operation. A reference generator circuit (134) is used for generating a reference output voltage corresponding to a lower erased state threshold voltage level. A switching circuit (P1, N1) is used to selectively disconnect a program current source of approximately 5 mu A from the selected certain ones of the columns of array bit lines containing the selected memory core cells which have been correctly programmed back. A sense logic circuit (26, 27) continuously compares a potential on one of the selected bit lines and the reference output voltage corresponding to the lower erase threshold voltage level.