发明名称 MATRIX CIRCUIT DETECTING FAILURE LOCATION IN COMMON SIGNAL
摘要 A matrix circuit includes, besides a plurality of common signal lines and a plurality of data signal lines arranged in a matrix, a plurality of monitoring signal lines that allow states of the common signal lines to be monitored. Inputs to the monitoring signal lines during one scan of the common signal lines are stored such that a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines is detected and a location of the faulty common signal line is identified based on the stored inputs to the monitoring signal lines.
申请公布号 US2016178689(A1) 申请公布日期 2016.06.23
申请号 US201514974465 申请日期 2015.12.18
申请人 FANUC Corporation 发明人 OKITA Hiroshi
分类号 G01R31/08 主分类号 G01R31/08
代理机构 代理人
主权项 1. A matrix circuit of a sink type having m (m is a natural number) common signal lines and n (n is a natural number) data signal lines, the common signal lines and the data signal lines being arranged in a matrix, and m×n switches each connected between the common signal line and the data signal line intersecting each other, the matrix circuit being configured such that states of keys are scanned by driving the common signal lines to a low level one by one while reading states of the data signal lines, the matrix circuit comprising: p (p is a natural number) monitoring signal lines that allow states of the common signal lines to be monitored; a storage unit in which inputs to the monitoring signal lines during one scan of the common signal lines are stored; and a detection unit that detects occurrence of a fault including a ground fault, a short circuit, or disconnection on any of the common signal lines to identify the faulty common signal line.
地址 Yamanashi JP