发明名称 |
Fet structure for minimum size length/width devices for performance boost and mismatch reduction |
摘要 |
Methods for preparing CMOS transistors having longer effective gate lengths and the resulting devices are disclosed. Embodiments include forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate between the spacers to form inner or outer sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench. |
申请公布号 |
US9379186(B1) |
申请公布日期 |
2016.06.28 |
申请号 |
US201514610140 |
申请日期 |
2015.01.30 |
申请人 |
GLOBALFOUNDRIES INC. |
发明人 |
Wang Qin;Chi Min-hwa;Zhao Meixiong;Shen Zhaoxu;Wang Haiting;Salazar Lucas M.;Yang Lan |
分类号 |
H01L21/302;H01L21/461;H01L29/10;H01L29/66;H01L29/423 |
主分类号 |
H01L21/302 |
代理机构 |
Ditthavong & Steiner, P.C. |
代理人 |
Ditthavong & Steiner, P.C. |
主权项 |
1. A method, comprising:
forming a dummy gate bound by spacers on opposing sides thereof, on a substrate; removing the dummy gate to form a trench between the spacers; modifying a gate channel portion of the substrate by anisotropically wet etching the gate channel portion of the substrate to form a concave channel with inner sidewalls; depositing a conformal high-k dielectric layer on the modified gate channel portion; and forming a metal gate in the trench. |
地址 |
Grand Cayman KY |