发明名称 Security device using high latency memory to implement high update rate statistics for large number of events
摘要 A security device includes a controller configured to determine a flow identifier and an event counter associated with a received data packet and a counter memory including multiple memory banks where each memory bank stores a partial counter value for one or more event counters. The counter memory is indexed by a counter identifier associated with the event counter. A memory controller selects a memory bank in the counter memory that was not the memory bank last selected and the partial counter value associated with the counter identifier in the selected memory bank is updated, the updated partial counter value being written back to the selected memory bank. In one embodiment, the partial counter value is updated and written back within the latency window of the memory bank last selected.
申请公布号 US9378784(B1) 申请公布日期 2016.06.28
申请号 US201313748493 申请日期 2013.01.23
申请人 Palo Alto Networks, Inc. 发明人 Vu De Bao;Saharia Gyanesh
分类号 G11C7/10;H04L12/861;G06F5/10 主分类号 G11C7/10
代理机构 Van Pelt, Yi & James LLP 代理人 Van Pelt, Yi & James LLP
主权项 1. A security device, comprising: a controller configured to receive incoming data packets and to determine a flow identifier associated with a received data packet, the controller further determining an event counter associated with the flow and providing a counter identifier to a memory controller; and a counter memory comprising a plurality of memory banks, each memory bank storing a partial counter value for one or more event counters, the counter memory being in communication with the memory controller and indexed by the counter identifier, wherein the memory controller marks the memory bank last selected and, in response to the memory controller receiving the counter identifier from the controller, the memory controller selects for access a single memory bank in the counter memory that was not marked as the memory bank last selected, the memory controller accessing the plurality of memory banks in the counter memory in any order with the same memory bank not being selected for access in consecutive counter updates, and the memory controller retrieves the partial counter value associated with only one counter identifier in the selected memory bank and the memory controller updates the partial counter value, the updated partial counter value being written back to the selected memory bank; and wherein the memory controller selects a first memory bank to update the partial counter value for a first counter identifier and marks the first memory bank, and the memory controller next selects a second memory bank not marked to update a partial counter value, the memory controller is configured to select a second counter identifier different from the first counter identifier to update the partial counter value in the second memory bank during the latency window of the update of the partial counter value of the first counter identifier.
地址 Santa Clara CA US