| 摘要 |
A precharge halt access mode system reduces the power consumed during sequential accesses of the memory cells within a memory block. During sequential accesses to the memory cells within a row of the memory block in a synchronous system, the bitlines within the memory are only precharged after the memory access to the last memory cell within the row is complete. After accesses to the other memory cells within the row, the precharging operation of the bitlines within the memory block is halted by a halt precharge logic circuit. Once the memory access to the last column within the memory block is detected the precharging of the bitlines is performed. During sequential accesses to the memory cells within a row in an asynchronous system, the bitlines within the memory block are only precharged during an access to the first memory cell within a row. A wordline disabling circuit will disable a wordline signal after an access to the first memory cell is complete. Each column includes a column gate which controls the accesses to each column and the activated memory cell. During a read operation, when a column gate is closed, the data on the bitlines of that column is coupled to inputs of a sense amplifier circuit. The sense amplifier circuit detects the sense of the data and generates an appropriate output. After each memory access operation to the memory block, the inputs to the sense amplifier are precharged. If a precharge halt access mode control signal is disabled the bitlines within a memory block are precharged after each memory access to the memory block. |
