| 摘要 |
A bus cycle control unit of a microprocessor includes a sizing register for latching designation of a 16-bit data bus, and a bus cycle detector for detecting necessity of an additional bus cycle on the basis of the condition of the bus cycle. A command decoder, coupled to the sizing register and the bus cycle decoder, selectively drives bus enable terminals of the bus cycle control unit, and generates various control signals, so that data is transferred through either both the MSB (most significant bits) 16 bits and the (least significant bits) LSB 16 bits of a 32-bit data bus terminal, or only the LSB 16 bits of the 32-bit data bus terminal. Thus, the microprocessor can be freely coupled to a data bus of a fixed 32-bit width, a data bus of a fixed 16-bit width, or a data bus having its data width which can be switched between 32 bits and 16 bits. |
