发明名称 |
Method of fabricating a stacked capacitor for a DRAM cell by plasma etching |
摘要 |
A DRAM memory capacitor is formed by depositing a layer of polysilicon on FOX and device areas. Form gate structures and S/D structures by etching through the oxide layer, so openings extend over a portion of the polysilicon layer of the gate structure and the FOX areas. Capacitor plates are formed next. Deposit a first plate into electrical and mechanical contact with one of the S/D structures and dope the first capacitor plate to a high level. Deposit a second plate doped to a low level, a third plate doped to a high level, and a fourth plate doped to a low level. Pattern the plates by etching so the remaining portions lie over planned capacitor areas, with the remainder removed by selective isotropic etching away of portions of the plates doped to a high level to provide fins by removal thereof from between plates doped to a low level. Remove by selective isotropic etching portions of the first plate and the third plate to create an undercut of the second and fourth plates to create fins of the second and fourth plates.
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申请公布号 |
US5721152(A) |
申请公布日期 |
1998.02.24 |
申请号 |
US19960766783 |
申请日期 |
1996.12.13 |
申请人 |
UNITED MICROELECTRONICS CORPORATION |
发明人 |
JENQ, J.S. JASON;HONG, GARY |
分类号 |
H01L21/02;H01L21/8242;H01L27/108;(IPC1-7):H01L2/824 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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