| 摘要 |
<p>PROBLEM TO BE SOLVED: To enable performing a test in a normal electric field and to improve reliability by enabling applying simultaneously the same potential to a drain terminal and a source terminal of a memory cell in testing soft erasing. SOLUTION: A ground potential (OV) is applied to all word lines W1-Wn of a memory cell array MCA in testing soft erasing, and a source bias potential is applied to a source line S1 by a sour voltage applying circuit SC. Each one end of bit lines D11-D1m is made an open state, and in each other end, a switch circuit DC is activated by a soft erasing test signal TSE, and a source bias potential is applied to each other end by a source voltage applying circuit SC. At this point, in memory cells M111-M1nm to be tested in soft erasing, a ground potential is applied to a control gate CG by word lines W1-Wn, a source bias potential is applied to a source terminal S by the source line S1, and a source bias potential is applied to a drain terminal by bit lines D11-D1m.</p> |
