发明名称 TRANSMISSION DATA TRIGGERED PIPELINE LATCH
摘要 PROBLEM TO BE SOLVED: To use data activated at valid time by using an input trigger inhibition means so as to inhibit the use of a relative input trigger when certain data are received by one of the input triggers. SOLUTION: During the clocks of a low level, when the data are received in latch inputs 406 and 408, the data inhibit the use of one of MOSFETs 424 and 426 operated by the data of reset inhibition means 425 and 426, the input triggers 412 and 413 are made usable and the MOSFETs 432 and 434 of the usable input triggers 412 and 413 receive logic HI for lowering corresponding data storage nodes 428 and 430 and store valid data in data storage means 416 and 417. At this point, (n) channel MOSFETs 440 and 442 connected between the ground of the input trigger inhibition means 414 and 415 and the input triggers 412 and 413 are operated by crossover connections 438 and 436 to the data storage nodes 430 and 428 in symmetrical control circuits 466 and 464.
申请公布号 JPH1055263(A) 申请公布日期 1998.02.24
申请号 JP19970105562 申请日期 1997.04.23
申请人 HEWLETT PACKARD CO <HP> 发明人 ROBAATO EICHI MIRAA JIYUNIA;SAMIYUERU DEII NAFUZUIGAA
分类号 G06F7/00;G06F9/38;H03K3/356 主分类号 G06F7/00
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