Transmission load control for multichannel HDLC TDM line

摘要

Output on Multiple Time Division Multiplexer (TDM) HDLC lines (28) is selectively and gracefully throttled. A throttling signal (99) is asserted whenever either the output FIFO queue (58) is almost full or the input FIFO queue (56) is almost empty. Whenever an in frame/out of frame state transition occurs for a given logical channel, a check is made whether throttling is required (292, 296). If throttling is required, an HDLC flag byte is transmitted (291, 299), delaying all such state transitions until the throttling signal (99) is no longer asserted.