Address decoder circuits adjusted for a high speed operation at a low power consumption

摘要

A decoder circuitry is provided between input signal lines and word lines. The number of the word lines is larger than the input signal lines. The decoder circuitry comprises a plurality of stages including at least an input side stage adjacent to the input signal lines and an output side stage adjacent to the word lines. Each of the plurality of stages includes plural logic circuits. The plural stages so vary as not to decrease in the number of the logic circuits when the stage approaches to the word lines so that the number of the logic circuits in the input side stage adjacent to the input signal lines is smaller than the number of the logic circuits in the output side stage adjacent to the word lines. Each of the logic circuits has a plurality of field effect transistors. The field effect transistors so vary as not to decrease in absolute value of threshold voltage when the stage approaches to the word lines so that an absolute value of threshold voltage of the transistors provided in the input side stage adjacent to the input signal lines is smaller than an absolute value of threshold voltage of the transistors provided in the output side stage adjacent to the word lines.