Gate driving circuit, display module and display device

摘要

Provided are a gate driving circuit, a display module and a display device belonging to the field of display technique and being designed for solving the problem of high power consumption of the display module in the prior art. The gate driving circuit is used for driving gates of TFTs corresponding to gate lines connected thereto, and includes at least two stages of shift registers connected in cascade, wherein each stage of shift register includes a first output terminal and a second output terminal, the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a corresponding gate line so as to apply a gate driving signal on the gates of TFTs through the corresponding gate line.

主权项

1. A gate driving circuit for driving gates of Thin Film Transistors TFTs corresponding to gate lines connected thereto, including:
at least two stages of shift registers connected in cascade, wherein each stage of shift register includes a first output terminal and a second output terminal, wherein the first output terminal is connected to an enable signal input terminal of a next stage of shift register so as to output a next stage enable signal to the next stage of shift register, and the second output terminal is connected to a corresponding gate line so as to apply a gate driving signal on the gates of TFTs through the corresponding gate line, wherein each stage of shift register includes a pull-up unit connected to a pull-up node, a first clock signal terminal, the first output terminal and the second output terminal, respectively, for, when a pull-up signal at a high level is detected, outputting a next stage enable signal to the next stage of shift register through the first output terminal and outputting the gate driving signal to the corresponding gate line through the second output terminal according to an first clock signal acquired; each stage of shift register further includes a pull-down unit connected to the pull-up node, a pull-down node, a second clock signal terminal and a low voltage maintaining terminal, respectively, for pulling-down a potential of the second output terminal and the potential of the pull-up node when a pull-down signal at a high level is detected and for pulling-down the potential of the second output terminal when a second clock signal at a high level is detected, wherein the second clock signal and the first clock signal are inverted to each other; each stage of shift register further includes a pull-down driving unit connected to the pull-down node, the pull-up node, the low voltage maintaining terminal and the second clock signal terminal, respectively, for outputting the pull-down signal at the high level when the second clock signal at the high level and the pull-up signal at a low level are detected.