SIGNAL LINE SELECTION CIRCUIT AND MATRIX TYPE DISPLAY DEVICE

摘要

PROBLEM TO BE SOLVED: To reduce the number of address lines and to reduce power consumption in a signal line selection circuit having counters and decoders divided in plural signal lines. SOLUTION: Related to three adjacent blocks BK1 -BK3 , a clock control circuit 21 in a block BK of a middle stage starts to supply a clock signal CK2 to a display counter 22 based on an output from a final output end of a display decoder 23 in the block BK1 of a preceding stage. Further, the same clock control circuit 21 stops to supply the clock signal CK2 based on the output from the first output end of the display decoder 23 in the block BK3 of a poststage.