| 摘要 |
PROBLEM TO BE SOLVED: To reduce largely the length of total wiring of a retrieving data line, to reduce the capacity of a bit line of a memory, and to increase reading/writing operation speed by dividing a memory cell array of one bit into plural columns. SOLUTION: The length of total wiring of a retrieving data line is largely reduced by dividing a memory cell array into four columns, in an associated memory consisting of (b)bits/4×n words. At the time of reading out, selected memory cell information is amplified and detected by reading/writing circuits 221-22b through pairs of bit line BL11-BLb4, column selecting circuit 211-21b, an outputted as read-out data D01-D0b. At the time of writing, input data Di1-Dib is written in a memory cell selected by reading/writing circuits 221/22b. As a data path used at the time of reading/writing operation is separated from a data path used at the time of comparison operation, these both operations never interfere each other.
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