| 摘要 |
PROBLEM TO BE SOLVED: To allow the circuit to easily detect a phase difference of two kinds of signals (horizontal synchronization signal HS and reference clock signal). SOLUTION: A decoder 12 decodes a count of a counter 11, counting the number of reference clock signals CK to produce a pulse P0 rising only for one clock period. The pulse P0 is stepwise delayed by a delay circuit 13 to produce a plurality of pulses P0-P9, having a prescribed phase differenceΔd. The state of a plurality of the pulses P0-P9 is received with a timing of a horizontal synchronization signal HS, and a phase difference of the horizontal synchronization signal HS is detected, with respect to the reference clock signal CK based on the change in the state. |
