发明名称 BOARD DEALING WITH NARROW PITCH LEAD TERMINAL AND HYBRID INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To prevent the generation of any solder bridging, by disposing alternately lead-terminal attaching lands with large widths and the ones with small widths on both the surfaces of a board, and by disposing the lead-terminal attaching land with small width on the rear surface present just under the one with large width for the front surface, and further, by disposing the lead-terminal attaching land with large width on the rear surface present just under the one with small width for the front surface. SOLUTION: In a lead-terminal attaching land portion present on the front surface of a board 1, lands 2 with 0.7mm widths and lands 3 with 0.4mm widths are disposed alternately at a first pitch. Similarly to the front surface, in a lead-terminal attaching land portion present on the rear surface of the board 1, lands 5 with 0.4mm widths and lands 4 with 0.7mm widths are disposed alternately at the same pitch as the first pitch. In the relation between the front and rear surfaces, the land with 0.7mm width and the land with 0.4mm width are also disposed to pair them. Squeezing lead terminals 6 with about 0.35mm widths respectively in between the lands 2, 5 and in between the lands 3, 4, they are fastened to each other by solder dipping. In the case of (1.0mm in pitch, and 0.7mm, 0.4mm in alternate attaching land widths) the generative rate of solder bridging phenomena can be made 0%.
申请公布号 JPH1051091(A) 申请公布日期 1998.02.20
申请号 JP19960198962 申请日期 1996.07.29
申请人 NEC CORP 发明人 MASUI KEIJI
分类号 H05K1/11;H05K3/34;(IPC1-7):H05K1/11;H01R9/09 主分类号 H05K1/11
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