| 摘要 |
Critical speed paths through a latch-based logic circuit must contain at least one latch-to-latch combinational delay which exceeds the nominal phase time of the circuit. To identify this set of paths through latch-to-latch delays greater than the nominal phase time of the circuit (i.e., through interesting tLLs), a half-path joining approach is employed. Backward half-paths from fixed timing points forward through the network defined by a latch abstraction of the circuit to an interesting tLL are multiplicatively joined with forward half-paths from the interesting tLL forward to other fixed timing points to form a set of fixed-point-to-fixed-point (F2F) paths through the interesting tLL. Timing analysis is performed on the set of F2F paths to identify those which represent critical speed paths through the circuit. The half-path joining approach is improved by performing timing analysis on the half-paths prior to combining. Based on the results of half-path timing analysis, the number of half-paths, and therefore the number of F2F paths resulting from a multiplicative joining of half-paths, is greatly reduced. One approach is to discard any half-path which is guaranteed to meet a target frequency. An enhancement is to identify at most two backward and two forward half-paths by identifying the worst half-path in each direction based on optimistic and pessimistic assumptions concerning time borrowing across the join point. A further enhancement is to perform only the pessimistic timing analysis. Although the purely pessimistic approach tends to favor failing path segments near the join point, any failing path segment which is "missed" because of the optimization is guaranteed to be found in another timing check because the "missed" segment must itself contain an interesting tLL.
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