发明名称 |
SHARED BW ARCHITECTURE FOR APPLICATIONS WITH VARYING LEVELS OF INTEGRITY REQUIREMENTS |
摘要 |
Communications systems architecture using a single shared resource bus to interconnect a plurality of subsystems each handling information having a first predetermined importance level and an error detect wrapper for encoding information to and from each such subsystem to detect errors in transmission along the shared resource bus. A heartbeat monitor is also provided for use in those subsystems handling information having a second predetermined level of importance to disable the subsystem if an error occurs within the subsystem.
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申请公布号 |
WO9807080(A1) |
申请公布日期 |
1998.02.19 |
申请号 |
WO1997US13515 |
申请日期 |
1997.07.31 |
申请人 |
HONEYWELL INC. |
发明人 |
FYE, JAMES, C. |
分类号 |
G06F13/36;G05D1/00;G06F11/00;G06F11/14;G06F13/00;G06F13/40;(IPC1-7):G05D1/00 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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