Integrated semiconductor memory array with buried plate electrode

摘要

An integrated semiconductor memory array has identical memory cells, each having (a) a selection transistor with source and drain regions (4, 6) within a semiconductor body (12) and a gate (8) within an insulation layer (10) on the semiconductor body (12); and (b) a storage capacitor with a dielectric (20) between a first electrode (16), in conductive connection with the source region (4), and a second electrode (18), in conductive connection with a common plate (14) located below the source region (4). The capacitor is located on the side faces of an insulation layer opening (26) above the source region (4). Also claimed is a process for producing the above array by (i) producing the common plate (14) preferably by deep dopant implantation into a semiconductor body (12); (ii) forming the transistor array by producing doped source and drain regions (4, 6) in the semiconductor body and gates (8) in the overlying insulation layer (10); (iii) etching openings (2 6) in the insulation layer above the source regions (4); (iv) applying first electrodes (16) onto the opening side faces; (v) further etching the openings (26) through the source regions (4) and the semiconductor body (12) down to the common plate (14) to form second openings (29); (vi) depositing a dielectric (20) and a second electrode (18) onto each first electrode (16) and onto the side faces of each second opening (29); and (vii) filling the interspace within each second electrode (18) with conductive material to produce a conductive connection (24).