| 摘要 |
<p>A failure analysis memory which operates at high-speed is provided by using a DRAM of a slow operation. A fail data compression section (13) for reducing the fail data writing frequency even when fail occurs in an address, which is accessed many times, in a nearby test cycle is provided. By this fail data compression section, the fail data writing frequency is reduced, and the number of interleave of a failure analysis memory as well, whereby a failure analysis memory is constituted of a small number of memory elements.</p> |
