An arrangement for supplying phase locked clock signals to semiconductor circuits

摘要

A semiconductor integrated circuit has first and second delay controllers (21, 22) for receiving an input signal (CLK), a plurality of object circuits ( 50 to 57) for receiving an internal signal from the first delay circuit (21) through a real line (41), and a phase comparator (3). The phase comparator receives the input signal and a dummy internal signal from the second delay controller (22) through a dummy line (42), and compares the phases of the received signals with each other. Further, the phase comparator controls delays in the first and second delay controllers according to the comparison result. The length of the real line (41) from the first delay controller (21) to any one of the object circuits (50 to 57) is substantially identical, and a load value of the dummy line (42) is substantially equal to that of the real line (41) between the first delay controller (21) and any one of the object circuits (5; 50 to 57). Therefore, each of the object circuits or pads receives a phase-locked control signal without regard to the physical position thereof.