| 摘要 |
<p>A memory device 12 with arithmetic logic processing (ALP) capability comprises a memory bus 16 connected to external terminals, a memory section 13 and an ALP section 14 for performing a processing on at least part of the data stored in the memory section in response to a first instruction inputted via the memory bus and for outputting the result onto the memory bus in response to a second instruction inputted via the memory bus. The first instruction may be a write instruction and the second instruction a read instruction. Alternatively the first instruction may be a coprocessor start operation and the second instruction a coprocessor synchronize operation. The memory device may include a storage section for at least a macro code which is executed by the first instruction. The device is used in a main memory system, which may also include memories 11 which do not include an ALP section. The two types of memory may have the same terminal structure.</p> |
