发明名称 |
Scan-bypass architecture without additional external latches |
摘要 |
A scan architecture for testing integrated circuit chips containing scannable memory devices, such as register arrays, is operable in a bypass mode during which only a small portion of the memory cells in each device or array is inserted in the scan path to substantially reduce scan path length, test time and test data volume during testing of other logic components in the circuit chip. Additional decoder logic is employed to select a small number of words in the device or array during the scan-bypass mode, and multiplexor circuitry removes the bypassed words from the scan path. By leaving the small number of the register array words in the scan path, observability of logic upstream of the array, and controllability of logic downstream of the array, is preserved during the bypass mode without the need for additional shift register latches and other external logic components. |
申请公布号 |
US5719879(A) |
申请公布日期 |
1998.02.17 |
申请号 |
US19950577676 |
申请日期 |
1995.12.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GILLIS, PAMELA SUE;KOLAGOTLA, RAVI KUMAR;MILLER, DENNIS A.;NOACK, MARIA;OAKLAND, STEVEN FREDERICK;REBEOR, CHRIS JOSEPH;SOPCHAK, THOMAS GREGORY;TRINKO-MECHLER, JEANNE |
分类号 |
G01R31/3185;G11C29/32;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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