发明名称 |
Adder circuit incorporating byte boundaries |
摘要 |
In accordance with the present invention, an adder is disclosed which combines byte boundary control signals with propagate-generate signal pairs immediately resulting from bit pairs of the input signals. Combining the byte boundary control signals with the first level propagate-generate signal pairs, rather than combining the byte boundary control signals with propagate-generate signal pairs indicative of the carry-out of a byte, allows the adder to utilize a more efficient tree signal path topology in which multiple levels of circuitry may be eliminated, thereby resulting in a reduction in propagation delay.
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申请公布号 |
US5719802(A) |
申请公布日期 |
1998.02.17 |
申请号 |
US19950577032 |
申请日期 |
1995.12.22 |
申请人 |
CHROMATIC RESEARCH, INC. |
发明人 |
PURCELL, STEPHEN C.;THOMSON, JOHN SHELDON |
分类号 |
G06F7/50;G06F7/508;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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