发明名称 CLOCK CIRCUIT
摘要 PROBLEM TO BE SOLVED: To eliminate the degradation of clocks for observing a phase and to accurately adjust the phase by dividing going and coming clock supply paths into plural and connecting them by a circuit for shaping the waveform of the clocks. SOLUTION: External clocks are inputted to a buffer A and outputted through a clock supply path A, the buffer B, the clock supply path B, the buffer C, the clock supply paths C and D, the buffer D, the clock supply path E, the buffer E and the clock supply path F. At the time, the buffers B-E respectively shape and transfer the clocks passed through the clock supply paths A-E and degraded. A phase adjustment device 21 (23) observes the clocks passed through a point A (B) and the point F (E), inputs the clocks passed through the point A (B) and delays the phase until it matches with the phase of the point F (E). Then, the clocks for which the clocks passed through the point A (B) are delayed for the time which is the half of a delay amount when the phase matches are outputted to a circuit part 22 (24).
申请公布号 JPH1039944(A) 申请公布日期 1998.02.13
申请号 JP19960193273 申请日期 1996.07.23
申请人 FUJITSU LTD 发明人 ASADA YOSHIMI
分类号 G06F1/10;G11C11/407;H03K5/125 主分类号 G06F1/10
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