| 摘要 |
<p>PROBLEM TO BE SOLVED: To immediately perform a processing no matter what kind of an operation mode a reset request is generated in, and to protect the contents of a memory by outputting respectively specified signals at the time of power supply OFF, at the time of a CPU operation mode and at the time of a CPU standby mode by a reset control circuit. SOLUTION: A CPU 1 outputs bus cycle signals to this reset control circuit 8 and inputs reset request signals from the reset control circuit 8. The reset control circuit 8 outputs system reset signals at all times regardless of the presence/absence of the reset request signals at the time of the power supply OFF, outputs the system reset signals asynchronized with the reset request signals and synchronized with a CPU bus cycle at the time of the CPU operation mode and outputs the system reset signals synchronized with the reset request signals at the time of the CPU standby mode. Thus, no matter what timing a reset SW 10 is depressed at, memory access does not become abnormal.</p> |
